1. Field of the Invention
This invention relates to complementary metal-oxide semiconductor (CMOS) manufacturing, and, more particularly, to a dual-polysilicon (dual-poly) gate fabrication method.
2. Description of the Related Art
Dual-poly gate technology is preferred to produce surface channel devices having small critical dimension (CD), e.g. CDs below approximately 0.25 micrometer (xcexcm). Such surface channel devices have both N-type and P-type material formed separately by masked implants to a common thin film of polysilicon deposited on a substrate. During gate formation by etching, using a single mask for both the N and P features, the N and P materials respond to etching chemistries differently, i.e. the result is differential etching of the materials. This leads to undesirably and often unacceptably different feature profiles and oxide remnant between the P and N regions of the gate.
The invented method involves separately etching the P and N gate features in a dual-poly gate using dual masks, thereby permitting the etching chemistries to be tuned to the differentially responsive P and N materials that form the gate. The method involves a) providing a polysilicon layer of a first type over a first region of a semiconductor substrate; b) providing a polysilicon layer of a second type over a second region of the semiconductor substrate; c) depositing a metallic layer overlying the polysilicon layers in the first and second regions; d) depositing an anti-reflective layer overlying the metallic layer in the first and second regions; e) selectively etching the dielectric hard-mask multi-layer film to form a patterned outer hard-mask multi-layer; f) forming a first photoresist pattern overlying the patterned outer hard-mask multi-layer in the first region; g) first etching the metallic layer and the polysilicon layer of the second type to form a stacked gate structure in the second region; h) forming a second photoresist pattern overlying the patterned outer hard-mask multi-layer in the second region; and i) second etching the metallic layer and the polysilicon layer of the first type to form a stacked gate structure in the first region. Preferably, the first photoresist pattern and the second photoresist pattern define a nominal boundary therebetween, with the patterns having a predefined gap therebetween in a region around the boundary. Alternatively, the dual-mask technique is used on a non-hardmask dual-poly film stack and the top dielectric multi-layer film is replaced by an ARC film.